This invention relates, in general, to vertical field effect transistors, and more particularly, relates to the structural arrangement of a vertical field effect transistor (FET) in order to achieve improved characteristics.
Vertical FETs are emerging as the preferred design of power transistors, particularly power FETs. In a vertical FET device the gate and source electrodes are on one surface of a semiconductor substrate and the drain electrode is on the opposite surface of the semiconductor substrate. The vertical FET device is a multi-celled structure having a given number of elementary cells connected in parallel in a semiconductor substrate. The multiple cells are arranged adjacent to each other and have a simple geometric form. These geometric forms refer to the source which is an enclosed source and wherein the geometries can be circles, squares, hexagons, etc. Even though there is no universal agreement on the optimum source geometry, it appears that hexagonal cells appear to have been the preferred geometric pattern.
The top surface of the semiconductor substrate which contains the gate and source electrodes, has at least two layers of interconnect metallization lines. The lower layer is typically polysilicon and forms the gate electrode while the upper layer, which can cover the entire top surface, is aluminum or an aluminum alloy and contacts the source regions individually. The reason the source regions are arranged in multiple cells is to provide maximum perimeter of the source areas. An important factor in FET devices is the on resistance of the FET device when it is in the conductive state. Therefore, it would be advantageous to have a power FET arrangement which would provide low on-resistance and make maximum use of the semiconductor surface area.
Accordingly, it is an object of the present invention to provide a vertical field effect transistor having a plurality of source areas which are arranged in a pattern to achieve a minimum of inactive drain area on the same surface of a semiconductor substrate as the source areas.
Another object of the present invention is to provide a field effect transistor which has reduced gate to drain capacitance.
Yet another object of the present invention is to provide a field effect transistor which has more active cells per unit area.
A further object of the present invention is to provide a vertical field effect transistor having low on resistance achieved through the arrangement of source areas.
Yet a further object of the present invention is to provide a power field effect transistor which has a greater channel width or perimeter per unit area of silicon thereby resulting in a field effect transistor having a greater gain.